UCETXINT=UCETXINT_0, UCSWACK=UCSWACK_0, UCGLIT=UCGLIT_0, UCSTPNACK=UCSTPNACK_0, UCASTP=UCASTP_0, UCCLTO=UCCLTO_0
eUSCI_Bx Control Word Register 1
| UCGLIT | Deglitch time 0 (UCGLIT_0): 50 ns 1 (UCGLIT_1): 25 ns 2 (UCGLIT_2): 12.5 ns 3 (UCGLIT_3): 6.25 ns |
| UCASTP | Automatic STOP condition generation 0 (UCASTP_0): No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don’t care. 1 (UCASTP_1): UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 2 (UCASTP_2): A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold |
| UCSWACK | SW or HW ACK control 0 (UCSWACK_0): The address acknowledge of the slave is controlled by the eUSCI_B module 1 (UCSWACK_1): The user needs to trigger the sending of the address ACK by issuing UCTXACK |
| UCSTPNACK | ACK all master bytes 0 (UCSTPNACK_0): Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 1 (UCSTPNACK_1): All bytes are acknowledged by the eUSCI_B when configured as master receiver |
| UCCLTO | Clock low timeout select 0 (UCCLTO_0): Disable clock low timeout counter 1 (UCCLTO_1): 135 000 SYSCLK cycles (approximately 28 ms) 2 (UCCLTO_2): 150 000 SYSCLK cycles (approximately 31 ms) 3 (UCCLTO_3): 165 000 SYSCLK cycles (approximately 34 ms) |
| UCETXINT | Early UCTXIFG0 0 (UCETXINT_0): UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 1 (UCETXINT_1): UCTXIFG0 is set for each START condition |